Herbert et al, U.S. Pat. No. 5,912,490 discloses a FET structure having a reduced drain to gate capacitance by providing a buried shield plate underlying the gate and between the gate and drain of the transistor. Use of a buried shield between the gate and drain of a field effect transistor can reduce gate to drain capacitance and maximizes the frequency response of the IGFETS.
As a result of this improvement in frequency response, the breakdown voltage of drain to substrate is lowered.
It appears that a compromise needs to be made between the reduction of gate to drain capacitance to increase the frequency response and the breakdown voltage of drain to substrate.
The goal of the invention is directed to a MOSFET structure having higher operation voltage and higher breakdown capability, while keeping a high frequency behaviour and a high density.